The present invention relates to a semiconductor device having a stressor or stress applying layer and a method for manufacturing the same.
As semiconductor memory devices are made smaller, existing MOSFET structures have been found to be inadequate in is providing a sufficient threshold voltage margin and refresh characteristics. Accordingly, various studies are being conducted to ensure the semiconductor device is provided with the sufficient threshold voltage as well adequate refresh characteristics, i.e., to counter the short channel effects.
One type of semiconductor devices uses a recess channel structure as a solution to the short channel effects experienced by the conventional lateral semiconductor device. The recess channel structure is a structure in which a channel area is recessed in U-shape to lengthen the effective channel length. This enables the device to minimize the short channel effects. Therefore, the recess channel structure is employed in many recent semiconductor devices.
Particularly, formation of a shallow junction has been used to ensure a Drain Induced Barrier Lowering (DIBL) margin according to a decrease in a channel length before the recess channel structure is suggested. Of course, even in this case, formation of a Punch Through Stop Layer through an ion implantation process to below the source and the drain for cutting off a drift current due to a strong electric field between a source and a drain is applied as a basic process.
However, because it is necessary to reduce a depletion area of the source and the drain through the shallow junction in order to form a channel length of nm range, a transistor having a three dimensional shape, such as, the recess channel structure, has been implemented recently.
In the recess channel structure, the current flows in a plurality of directions on a plurality of surfaces instead of in a single direction on a single surface as in the conventional transistor. One issue associated with the recess channel structure is that electron mobility may be inconsistent from one another.
Specifically, FIG. 1 is a cross-sectional view illustrating a conventional MOSFET device having a recess channel structure, FIG. 2 is a view for explaining a crystal plane and a current flow and FIG. 3 is a graph for explaining an electron mobility according to the crystal plane. With reference to the drawings, description to the conventional MOSFET device having a recess channel structure will be made.
Referring to FIG. 1, an isolation layer 104 for defining active areas 102 is formed on a semiconductor substrate 100, a recess R is formed in the active area 102, a gate 120 is formed on the recess R and source/drain areas 122 are formed in a surface of the active area 102 at both sides of the gate 120.
In FIG. 1, a reference symbol 108 denotes a threshold voltage adjusting area, 110 denotes a gate insulation layer, 112 denotes a polysilicon layer, 114 denotes a metal based layer, 116 denotes a hard mask layer and 118 denotes a gate spacer.
The MOSFET device having such recess channel structure is generally formed on the semiconductor substrate 100 consisting of silicon lattices on the basis of a surface (110). Further, unlike current flows in a single direction <110> on the surface (100) in a planar MOSFET device, is as shown in FIG. 2, at least two types of current exist in the MOSFET device having the recess channel structure formed on the semiconductor substrate 100 on the basis of the surface (110), i.e., a current flow A flowing in the direction <110> along the surface (100) at a bottom of the recess and a current flow B flowing in a direction <100> along the surface (110) at a side surface of the recess. At this time, the current flow in the MOSFET device having the recess channel are in a sequence of (110)/<100>, (100)/<110> and (110)/<100>.
Comparing the two current flows occurring in the MOSFET device having the recess channel, as shown in FIG. 3, it can be appreciated that an electron mobility in the current flowing horizontally along the bottom of the recess, i.e. flowing direction <110> along surface (100) is larger than an electron mobility in the current flowing vertically along the side surface of the recess, i.e. flowing direction <100> along surface (110).
Therefore, an electron mobility in the MOSFET device having the recess channel is generally determined by the electron mobility in the current flowing horizontally along the bottom of the recess, i.e. flowing direction <110> along surface (100).
However, in the MOSFET device having the recess channel, the low electron mobility in the current flowing vertically along the side surface of the recess, i.e. flowing direction <100> along surface (110) causes a slow operation speed, particularly a slow writing time. Therefore, the electron mobility in the current flowing direction <100> along surface (110) should be increased to improve the operation speed of the MOSFET device having the recess channel.